SSA-AC: Static Significance Analysis Framework towards Approximate Computing

We have developed a framework to conduct static analysis on a software application code towards approximate computing, called SSA-AC. The framework internally utilizes an existing symbolic analysis tool, KLEE, to extract the exectuion paths of the program and the output expressions composed of the independent inputs and variables along with the paths and generates the significance ranking of those independent inputs and variables to suggest the users to find which variables may be more significant (less tolerable to the approximation or have more impacts on the output quality).

    Source Code (released in 2019)

    Published Paper

  • Sara Ayman Metwalli and Yuko Hara-Azumi, "SSA-AC: Static Significance Analysis for Approximate Computing," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2019.

SubRISC: Simple Instruction-Set Computer for IoT edge devices

We have developed a small and energy-efficient RISC processor, called SubRISC, which has the limited number of simple instructions extended from Subtract and branch on NeGative with 4 operands (SNG4). The processor is described in synthesizable Verilog HDL by Synopsys Design Compiler.

    Source Code (released in 2018)

    Published Paper

  • K. Saso and Y. Hara-Azumi, "Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices," In Proceeding of 29th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, Jul. 2018.

SUBLEQ Toolchain

Noriaki will add the description.

    Source Code (released in 2015)

    Published Paper

  • T. Ahmed, N. Sakamoto, J. Anderson, & Y. Hara-Azumi, "Synthesizable-from-C Embedded Processor based on MIPS ISA and OISC" In Proceeding of IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), pp.114-123, Porto, Portugal, Oct. 2015.

Hirundo: Synthesizable-from-C Embedded Processor

The processor is described in synthesizable C by LegUp (from University of Toronto) or Vivado HLS (from Xilinx) tools to generate its RTL description. The processor contains a host MIPS processor and a small SUBLEQ co-processor which emulates any operations in absence of hardware resources on the host processor. In addition, the framework contains a built-in profiler to ease the developer to analyze the program and customize the processor for specific applications.


    Source Code (released in 2015)

    Published Paper

  • T. Ahmed, N. Sakamoto, J. Anderson, & Y. Hara-Azumi  "Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC" In Proceeding of IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), pp.114-123, Porto, Portugal, Oct. 2015.
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